In the development of integrated circuits, particularly very large scale integrated circuits, it is desirable to reduce the number of design/prototype iterations. One tool available to circuit designers used to minimize the prototyping needed to validate performance of circuit designs is modeling and simulation. Modeling and simulation may be performed at various levels of circuitry, from complex networks down to individual elements, devices or even portions thereof.
In the simplest sense models are mathematical representations of certain performance characteristics of the device being modeled. Simulations rely upon these models and specific predetermined device parameters which correspond to model parameters. Simulations solve the model equations, alone or in combination with a network of other models. Some models are utilized by circuit designers to define a device as part of a circuit to evaluate a circuit performance. Other models may be utilized by a designer of a device in order to model and simulate the device itself through manipulation of certain parameter variables.
Relatively speaking, diode or semiconductor junction models are among the simplest of semiconductor device models. Junction models include formulas to calculate steady-state current vs. voltage (I-V characteristics), and charge storage within the device (typically, a nonlinear capacitance vs. applied voltage). Steady state current can usually be modeled well using the classical SPICE formula. In its basic form, the formula models current to increase substantially exponentially with forward voltage. The model also includes a parasitic series resistance term or parameter (series resistance).
The general form of such a model may be expressed as follows:                ID=IS(eq(VDx−IDRtotal)/nkT−1), or alternatively through rearrangement as        
            V      Dx        =                            nkT          q                ⁢                  ln          ⁡                      (                                                            I                  D                                                  I                  S                                            +              1                        )                              +                        I          D                ×                  R          total                      ,wherein;                VDx is voltage across the semiconductor device (device voltage),        ID is current through the semiconductor device (device current),        IS is the semiconductor device reverse saturation current,        Rtotal is the semiconductor device lumped parasitic series resistance (series resistance),        n is the emission coefficient,        k is the boltzman constant        T is temperature, and        q is the electronic charge.        
An even more simplified model equation may be expressed asVDx=VD+IDRtotal, wherein                VD is a semiconductor junction voltage,        VDx is a semiconductor device voltage,        ID is a semiconductor device current, and        Rtotal is the semiconductor device lumped parasitic series resistance (series resistance).        
Certain models also have a variety of parameters to describe avalanche breakdown current or AC response, which parameters are not specifically called out in the above equations nor further addressed herein.
Typically, the basic SPICE model for a junction device is adequate to obtain reasonably good results. Of course, a model's fidelity is always dependent upon its parameter values and extraction techniques. The exponential nature of the junction model equations together with compromises in extraction techniques and parameter assumptions result in compromised accuracy, particularly in the so-called forward biased high current or knee region of the current-voltage characterization curve. A classic extraction technique and associated assumption regarding the series resistance of a semiconductor junction device relies upon defining the series resistance as a simple fixed value equaling sheet resistance divided by the active area of the device. FIG. 1 illustrates such a typical shortfall at 10 when such parasitic extraction technique is followed wherein modeled results (solid line) are shown to deviate from measured results (data points) on a typical linear scale of device voltage (V) versus device current (ID). Such an assumption regarding the relationship between series resistance and active area geometry will result in additional errors if carried through to modeling and simulation directed toward scaling devices and simulations of scaled devices.
Therefore, what is needed is an improved method of modeling the parasitic resistance of a semiconductor junction device, particularly in the high current region of operation. What is also needed is an improved manner of simulating a semiconductor junction device having improved fidelity and accuracy.